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64k x 32 static ram 11403 west bernardo court, suite 100, san diego, ca92127. tel (858) 674 2233, fax no. (858) 674 2230 e-mail: sales@mosaicsemi.com 64k x 16 64k x 16 /bs3 /bs2 /bs1 /bs0 /cs2 /cs1 /oe /we d0~15 d16~31 a0~17 description si g nal address input a0~a15 data input/output d0~d31 chip select / cs1~2 b y te select / bs0~3 write enable / we output enable / oe no connect nc power v cc ground v ss pin functions block diagram pin definition see page 2. package details puma 68 - plastic 68 j leaded package max. dimensions - 0.988 x 0.988 x 0.200 features ? access times of 12, 15, 17 or 20ns. ? 5v + 10%. ? commercial and industrial temperature grades ? 68 j lead suface mount package. ? jedec standard footprint. ? user configurable as 8 / 16 / 32 bits wide ? operating power (32 bit) 2.31w (max) ? low power standby. (ttl) 330mw (max) (cmos) 83mw (max) puma 68s2000x - 012/015/017/020 issue 5.1 august 1999 description the puma68 range of devices provide a high density surface mount industry standard memory solution which may accommodate various memory technologies including sram, eeprom and flash. the devices are designed to offer a defined upgrade path and may be user configured as 16 or 32 bits wide. the puma68s2000x is a 64kx32 sram module housed in a 68 jleaded package which complies with the jedec 68 plcc standard. access times of 12, 15, 17 and 20ns are available. the 5v device is available to commercial and industrial temperature grade. 128kx32 and 256kx32 and 512kx32 sram puma68 devices are available in the same footprint to offer a defined upgrade path.
issue 5.1 august 1999 page 2 pin definition - puma68s2000x pin si g nal pin si g nal 1 v cc 35 v cc 2 /cs2 36 a13 3 /bs0 37 a12 4 /bs1 38 a11 5 /bs2 39 a10 6 /bs3 40 a9 7 nc 41 a8 8 nc 42 a7 9 d16 43 d0 10 d17 44 d1 11 d18 45 d2 12 d19 46 d3 13 v ss 47 v ss 14 d20 48 d4 15 d21 49 d5 16 d22 50 d6 17 d23 51 d7 18 v cc 52 v cc 19 d24 53 d8 20 d25 54 d9 21 d26 55 d10 22 d27 56 d11 23 v ss 57 v ss 24 d28 58 d12 25 d29 59 d13 26 d30 60 d14 27 d31 61 d15 28 a6 62 a14 29 a5 63 a15 30 a4 64 nc 31 a3 65 /we 32 a2 66 /oe 33 a1 67 /cs1 34 a0 68 nc
dc operating conditions issue 5.1 august 1999 page 3 parameter s y mbol min t y p max unit suppl y volta g e v cc 4.5 5.0 5.5 v input hi g h volta g e v ih 2.2 - v cc +0.3 v input low volta g e v il -0.3 - 0.8 v operatin g temperature ( commercial ) t a 0 - 70 o c ( industrial ) t ai -40 - 85 o c absolute maximum ratings (1) recommended operating conditions dc electrical characteristics (v cc =5v +10%, t a =0 o c to +70 o c) parameter s y mbol min max unit volta g e on an y pin relative to v ss v t ( 2 ) -0.3 to +7.0 v power dissipation p t 2.0 w stora g e temperature t stg -55 to +125 o c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability (2) v t can be -2.0v pulse of less than 10ns notes : typical values are at v cc =5.0v, t a =25 o c and specified loading. parameter s y mbol test condition min t y p max unit input leaka g e current address, /oe , /we i li 0v < v in < v cc -4 - 4 m a output leakage current i lo / cs1~2=v ih , v i/o =gnd to v cc -4 - 4 m a operating supply current (2) 32 bit i cc1 min. cycle, / cs1~2=v il ,v il v cc -0.2v, 0.2v issue 5.1 august 1999 page 4 capacitance (v cc = 5.0v +10%, t a = 25 o c) test conditions output load ? input pulse levels : 0v to 3.0v ? input rise and fall times : 3ns ? input and output timing reference levels : 1.5v ? output load : see load diagram. ?v cc = 5v +10% note : these parameters are calculated not measured. 645w 100pf i/o pin 1.76v parameter s y mbol test condition min t y p max unit input capacitance , ( address, /oe, /we ) c in1 v in =0v - - 20 pf i/p capacitance , ( other ) c in2 v in =0v 10 i/o capacitance , ( 16 bit mode - worst case ) c i/o v i/o =0v - - 24 pf
issue 5.1 august 1999 page 5 operation truth table notes : h=v ih : l=vi l : x=v ih or v il /cs1 /cs2 /bs0 /bs1 /bs2 /bs3 /oe / we suppl y current mode l l l h h h x l i cc1 write d0~d7 l l h l h h x l i cc1 write d8~d15 l l h h l h x l i cc1 write d16~d23 l l h h h l x l i cc1 write d24~d31 l l l l h h x l i cc1 write d0~d15 l l h h l l x l i cc1 write d16~d31 l l l l l l x l i cc1 write d0~d31 l l h h h h x l i cc1 d0~d31 , hi g h z l l l h h h l h i cc1 read d0~d7 l l h l h h l h i cc1 read d8~d15 l l h h l h l h i cc1 read d16~d23 l l h h h l l h i cc1 read d24~d31 l l l l h h l h i cc1 read d0~d15 l l h h l l l h i cc1 read d16~d31 l l l l l l l h i cc1 read d0~d31 l l x x x x h h i cc1 d0~d31 hi g h-z l h l l x x x l i cc2 write d0~d15 , d16~31 standb y l h l h x x x l i cc2 write d0~d7 , d16~31 standb y l h h l x x x l i cc2 write d8~d15 , d16~31 standb y l h h h x x x l i cc2 d0~d15 high-z, d16~31 standb y l h x x x x h h i cc2 d0~d15 high-z, d16~31 standb y h l x x l l x l i cc2 d0~15 standb y, write d16~31 h l x x l h x l i cc2 d0~15 standb y, write d16~23 h l x x h l x l i cc2 d0~15 standb y, write d24~31 h l x x h h x l i cc2 d0~15 standby, d16~31 hi g h h l x x x x h h i cc2 d0~15 standby, d16~31 hi g h z h h x x x x x x i sb1 , i sb2 d0~d31 standb y
ac operating conditions issue 5.1 august 1999 page 6 12 15 17 20 parameter s y mbol min max min max min max min max units read c y cle time t rc 12 - 15 - 17 - 20 - ns address access time t aa - 12 - 15 - 17 - 20 ns chip select access time t acs - 12 - 15 - 17 - 20 ns b y te select access time t ba - 6 7 - 8 - 9 ns output enable to output valid t oe - 6 - 7 - 8 - 9 ns output hold from address chan g e t oh 3 - 3 - 3 - 3 - ns chip selection to output in low z t clz 3 - 3 - 3 - 3 - ns b y te selection to output in low z t blz 0 - 0 - 0 - 0 - ns output enable to output in low z t olz 0 - 0 - 0 - 0 - ns chip deselection to output in hi g h z t chz 0 6 0 7 0 8 0 9 ns output disable to output in hi g h z t ohz 0 6 0 7 0 8 0 9 ns b y te deselction to output in hi g h z t bhz 0 6 0 7 0 8 0 9 ns read cycle write cycle 12 15 17 20 parameter s y mbol min max min max min max min max units write c y cle time t wc 12 - 15 - 17 - 20 - ns chip selection to end of write t cw 8 - 10 - 11 - 12 - ns b y te selection to end of write t bw 8 - 10 - 11 - 12 - ns address valid to end of write t aw 8 - 10 - 11 - 12 - ns address setup time t as 0 - 0 - 0 - 0 - ns write pulse width t wp 8 - 10 - 11 - 12 - ns write recover y time t wr 0 - 0 - 0 - 0 - ns write to output in hi g h z t whz 0 6 0 7 0 8 0 9 ns data to write time overlap t dw 6 - 7 - 8 - 9 - ns data hold time from write time t dh 0 - 0 - 0 - 0 - ns output active from end of write t ow 3 - 3 - 3 - 3 - ns
timing waveforms issue 5.1 august 1999 page 7 previous data valid data valid address data out t rc t aa t oh read cycle 1 (address controlled, /cs=/oe=v il , /we=v ih ) read cycle 2 (/we = v ih ) high z data valid address data out t rc t aa t co t oe t olz t lz(4,5) t oh t hz(3,4,5) t bhz(3,4,5) /cs /ub,/lb /oe t blz(4,5) t ba t ohz notes (readcycle) 1. /we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device. 5. transition is measured 200mv from steady state voltage with load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with /cs=v il . 7. address valid prior to coincident with /cs transition low. 8. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
issue 5.1 august 1999 page 8 write cycle 1 (/oe = clock) /cs t cw(3) t bw address data out t wc t aw t wr(5) t as(4) t wp(2) t ohz(6) high z /we t dw t dh notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if /oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. /ub, /lb data in valid data /oe high z
issue 5.1 august 1999 page 9 write cycle 2 (/oe = low fixed) /cs address data out t wc t aw t wr(5) t cw(3) t as(4) t wp1(2) t whz(6) hi g h z /we t dw t dh t ow (10) (9) notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if /oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. /ub, /lb t bw data in hi g h z valid data
issue 5.1 august 1999 page 10 /cs address data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t whz(6) high z high z(8) /we valid data t dw t dh t lz high z high z notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if /oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. /ub, /lb t bw write cycle 3 (/cs = controlled)
issue 5.1 august 1999 page 11 write cycle 4 (/ub, /lb controlled) /cs address data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t whz(6) high z high z(8) /we valid data t dw t dh t blz high z notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if /oe, /cs and /we are in the read m ode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. /ub, /lb t bw
package details page 12 issue 5.1 august 1999 puma 68 pin jedec surface mount plcc pin 1 top view 25.02 (0.985) 25.27 (0.995) 0.90 (0.035) typ 23.11 (0.910) 5.0 8 (0.200) m ax 24.13 (0.950) 25.02 (0.985) 25.27 (0.995) 0.46 (0.018) 1.27 (0.050) 25.02 (0.985) 25.27 (0.995) pin 68
ordering information page 13 issue 5.1 august 1999 ordering information note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director. puma 68s2000x i - 015 speed 012 = 12ns 015 = 15ns 017 = 17ns 020 = 20ns temp. range/screening blank = commercial i = industrial power consumption blank = standard pinout configuration x = industry standard pinout memory organisation 2000 = configurable as 64k x 32 or 128k x 16 technology s = sram package puma 68 = 68 pin j leaded plcc http://www.mosaicsemi.com/
customer guidelines page 14 issue 5.1 august 1999 co planarity specified as +/- 2 thou max. visual inspection standard all devices inspected to ansi/j-std-001b class 2 standard moisture sensitivity devices are moisture sensitive. shelf life in sealed bag 12 months at <40 o c and <90% relative humidity (rh). after this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220 o c) must be : a : mounted within 72 hours at factory conditions of <30 o c/60% rh or b : stored at <20% rh if these conditions are not met or indicator card is >20% when read at 23 o c +/-5% devices require baking as specified below. if baking is required, devices may be baked for :- a : 24 hours at 125 o c +/-5% for high temperature device containers or b : 192 hours at 40 o c +5 o c/-0 o c and <5% rh for low temperature device containers . packaging standard devices packaged in dry nitrogen, jed-std-020. packaged in trays as standard. tape and reel available for shipment quantities exceeding 200pcs upon request. soldering recomendations ir/convection - ramp rate 6 o c/sec max. temp. exceeding 183 o c 150 secs. max. peak temperature 225 o c time within 5 o c of peak 20 secs max. ramp down 6 o c/sec max. vapour phase - ramp up rate 6 o c/sec max. peak temperature 215 - 219 o c time within 5 o c of peak 60 secs max. ramp down 6 o c/sec max. the above conditions must not be exceeded note : the above recomendations are based on standard industry practice. failure to comply with the above recommendations invalidates product warranty.

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